OS: Windows 64bit | Language: English | Size: 3.3 GB
Cadence Design Systems Ltd., a world-renowned provider of EDA software, has released update for Cadence SPB OrCAD 16.60, software a comprehensive package design of electronic circuits, analog and digital simulation, IC design of programmable logic and custom circuits, as well as the development and preparation for the production of printed circuit boards.

Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.

This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry's first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.

Whats New :

Fixed CCRs: SPB 17.2 HF020

CCRID Product ProductLevel2 Title

1737443 ADW DBEDITOR Revising the schematic model classification for one category causes all parts in the library to be revised
1734123 ALLEGRO_EDITOR 3D_CANVAS Interactive 3D canvas crashes Allegro PCB Designer in 17.2 S016
1742084 ALLEGRO_EDITOR DATABASE Running DB Doctor on DRA files with custom pad shapes resets some of the custom padstack shapes in release 17.2
1739397 ALLEGRO_EDITOR INTERACTIV In release 17.2, running the SKILL function axlImportXmlDBRecords causes Allegro PCB Editor to crash
1724588 ALLEGRO_EDITOR MANUFACT Backdrill Route keepout suppressing existing Route Keepouts
1740036 ALLEGRO_EDITOR MANUFACT Generating the cross-section chart does not provide information about the overall board thickness
1743726 ALLEGRO_EDITOR OTHER IDF file export: In release 17.2, only one design outline is exported as against multiple board outlines in release 16.6
1744467 ALLEGRO_EDITOR OTHER The 'logical_op_new' variable is not displayed in User Preferences Editor
1729350 ALLEGRO_EDITOR REPORTS Net loop report is not working.
1713014 ALLEGRO_EDITOR SHAPE Incorrect behavior of donut shaped pads at certain rotations
1739870 ALLEGRO_EDITOR SHAPE The artwork is different from the PCB in release 17.2 Hotfix 17
1698869 ALLEGRO_EDITOR SKILL PCB Editor crashes when trying to open another .brd file after running SRM on first .brd file
1739307 ALLEGRO_EDITOR SKILL axlCNSDFAExport fails after first run
1743385 ALLEGRO_EDITOR SKILL SKILL APIs for STEP model mapping are not available in release 17.2 Hotfix 17 or 18
1685826 ALLEGRO_EDITOR UI_GENERAL Reports when opened from Status Form disappear behind PCB Editor canvas when clicking on canvas
1687797 ALLEGRO_EDITOR UI_GENERAL Cannot open two HTML windows, one after the other, while using SKILL function
1696229 ALLEGRO_EDITOR UI_GENERAL Setting the 'allegro_html' environment variable in User Preferences Editor overwrites existing popup text windows
1708636 ALLEGRO_EDITOR UI_GENERAL In SPB 17.2 release, keyboard focus automatically shifts to the newly opened dialog box
1711367 ALLEGRO_EDITOR UI_GENERAL Launching two report windows using SKILL is not working in 17.2
1742856 ALLEGRO_EDITOR UI_GENERAL Allegro PCB Editor crashes if Project Manager is open for a design in release 17.2 Hotfix 18
1729519 APD SHAPE shape degassing does not generate all voids to cover entire shape
1711375 CONCEPT_HDL CORE Copy-paste of schematic between two instances of DE-HDL is not working as expected
1737230 CONCEPT_HDL CORE On the Linux platform, copying of schematic objects does not work between designs of releases 16.6 and 17.2
1741375 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol
1743992 CONCEPT_HDL CORE Inconsistent behavior of the Move command when moving a symbol
1736093 CONSTRAINT_MGR CONCEPT_HDL Incorrect topology extraction and mapping errors related to MUX parts
1743518 CONSTRAINT_MGR CONCEPT_HDL Lag observed in expanding and collapsing the net classes in Constraint Manager
1730159 FSP ALLEGRO_INTEG FSP diff engine does not read PF Thevenin connections in FSP
1664070 ORBITIO ALLEGRO_SIP_I Display pads of SMD components on correct layer
1709319 ORBITIO USABILITY OrbitIO issues an error about Device template while importing brd with Bundles
1741150 PSPICE ENVIRONMENT Need a way to prevent the 'pspSimSetting.[Misafirler Kayıt Olmadan Link Göremezler Lütfen Kayıt İçin Tıklayın ! ]